Manish Kumar Jaiswal, Hayden Kwok-Hay So. Dual-mode double precision / two-parallel single precision floating point multiplier architecture. In 2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015. pages 213-218, IEEE, 2015. [doi]
@inproceedings{JaiswalS15,
title = {Dual-mode double precision / two-parallel single precision floating point multiplier architecture},
author = {Manish Kumar Jaiswal and Hayden Kwok-Hay So},
year = {2015},
doi = {10.1109/VLSI-SoC.2015.7314418},
url = {http://dx.doi.org/10.1109/VLSI-SoC.2015.7314418},
researchr = {https://researchr.org/publication/JaiswalS15},
cites = {0},
citedby = {0},
pages = {213-218},
booktitle = {2015 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
publisher = {IEEE},
isbn = {978-1-4673-9140-5},
}