Table of Contents

• Message from the technical program chairsYoungsoo Shin, Chi-Ying Tsui. [doi]
• Message from the general chairsNaehyuck Chang, Kiyoung Choi. [doi]
• An Incremental Timing-Driven flow using quadratic formulation for detailed placementGuilherme Flach, Jucemar Monteiro, Mateus Fogaca, Julia Casarin Puget, Paulo F. Butzen, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis. 1-6 [doi]
• Flare reduction in EUV Lithography by perturbation of wire segmentsSudipta Paul, Pritha Banerjee, Susmita Sur-Kolay. 7-12 [doi]
• Analysis and testing on delays with two time framesMasahiro Fujita. 13-18 [doi]
• Contactless transmission of intellectual property data to protect FPGA designsLilian Bossuet, Viktor Fischer, Pierre Bayon. 19-24 [doi]
• Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC coresMichael Gautschi, Andreas Traber, Antonio Pullini, Luca Benini, Michele Scandale, Alessandro Di Federico, Michele Beretta, Giovanni Agosta. 25-30 [doi]
• Design of asynchronous RISC CPU register-file Write-Back queueMatthew M. Kim, Karl M. Fant, Paul Beckett. 31-36 [doi]
• Modular performance analysis of Multicore SoC-based small cell LTE base stationManikantan Srinivasan, C. Siva Ram Murthy, Anusuya Balasubramanian. 37-42 [doi]
• Embedded low power analog CMOS Fuzzy Logic Controller chip for industrial applicationsManikandan Pandiyan, Geetha Mani. 43-48 [doi]
• Digital CMOS neuromorphic processor design featuring unsupervised online learningJae-sun Seo, Mingoo Seok. 49-51 [doi]
• An overview on memristor crossabr based neuromorphic circuit and architectureZheng Li, Chenchen Liu, Yandan Wang, Bonan Yan, Chaofei Yang, Jianlei Yang, Hai Li. 52-56 [doi]
• An equation-based battery cycle life model for various battery chemistriesAlberto Bocca, Alessandro Sassone, Donghwa Shin, Alberto Macii, Enrico Macii, Massimo Poncino. 57-62 [doi]
• Power-management high-level synthesisDominik Macko, Katarina Jelemenska, Pavel Cicak. 63-68 [doi]
• An optimal operating point by using error monitoring circuits with an error-resilient techniqueJaemin Lee, Seungwon Kim, Youngmin Kim, Seokhyeong Kang. 69-73 [doi]
• Dynamic error tracking and supply voltage adjustment for low powerPierre Nicolas-Nicolaz, Kiyoung Choi. 74-79 [doi]
• Physical design and mask optimization for directed self-assembly lithography (DSAL)Seongbo Shim, Youngsoo Shin. 80-85 [doi]
• Qualifying non-volatile register files for embedded systems through compiler-directed write minimization and balancingChengmo Yang, Maria Ruiz Varela. 86-91 [doi]
• Non-volatile memories in FPGAs: Exploiting logic similarity to accelerate reconfiguration and increase programming cyclesYuan Xue, Patrick Cronin, Chengmo Yang, Jingtong Hu. 92-97 [doi]
• Prefetch-based dynamic row buffer management for LPDDR2-NVM devicesJaehyun Park, Donghwa Shin, Hyung Gyu Lee. 98-103 [doi]
• Design space exploration of row buffer architecture for phase change memory with LPDDR2-NVM interfaceJaehyun Park, Donghwa Shin, Hyung Gyu Lee. 104-109 [doi]
• Architecture exploration of 3D FPGA to minimize internal layer connectionMotoki Amagasaki, Yuto Takeuchi, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi. 110-115 [doi]
• Compact interconnect approach for networks of neural cliques using 3D technologyBartosz Boguslawski, Hossam Sarhan, Frédéric Heitzmann, Fabrice Seguin, Sebastien Thuries, Olivier Billoint, Fabien Clermidy. 116-121 [doi]
• A thermal estimation model for 3D IC using liquid cooled microchannels and thermal TSVsSurajit Kumar Roy, Supriyo Mandal, Chandan Giri, Hafizur Rahaman. 122-127 [doi]
• An equilibrium partitioning method for multicast traffic in 3D NoC architectureLin Wei, Lei Zhou. 128-133 [doi]
• An integrated SoC for science data processing in next-generation space flight instruments avionicsXabier Iturbe, Didier Keymeulen, Emre Ozer, Patrick Yiu, Daniel Berisford, Kevin Hand, Robert Carlson. 134-141 [doi]
• Hardware architecture and optimization of sliding window based pedestrian detection on FPGA for high resolution images by varying local featuresAsim Khan, Muhammad Umar Karim Khan, Muhammad Bilal, Chong-Min Kyung. 142-148 [doi]
• 10Mbps human body communication SoC for BANHyungil Park, Ingi Lim, Sungweon Kang, Whan-Woo Kim. 149-153 [doi]
• Integrating wearable low power CMOS ECG acquisition SoC with decision making system for WSBN applicationsManikandan Pandiyan, Geetha Mani, Jovitha Jerome, Natarajan S. 154-158 [doi]
• Slack-aware timing margin redistribution technique utilizing error avoidance flip-flops and time borrowingMini Jayakrishnan, Alan Chang, José Pineda de Gyvez, Kim Tae Hyoung. 159-164 [doi]
• Circuit performance optimization for local intra-die process variations using a gate selection metricVíctor H. Champac, Alejandra Nicte-ha Reyes, Andres F. Gomez. 165-170 [doi]
• Scalable algorithm for structural fault collapsing in digital circuitsRaimund Ubar, Lembit Jurimagi, Elmet Orasson, Jaan Raik. 171-176 [doi]
• Cost reduction of system-level tests with stressed structural tests and SVMJing-Jia Liou, Meng-Ta Hsieh, Jun-Fei Cherng, Harry H. Chen. 177-182 [doi]
• Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAMNamhyung Kim, Junwhan Ahn, Woong Seo, Kiyoung Choi. 183-188 [doi]
• JAIP-MP: A four-core Java application processorChun-Jen Tsai, Tsung-Han Wu, Hung-Cheng Su. 189-194 [doi]
• Locality-aware vertex scheduling for GPU-based graph computationHyunsun Park, Junwhan Ahn, Eunhyeok Park, Sungjoo Yoo. 195-200 [doi]
• Traffic-aware buffer reconfiguration in on-chip networksRamin Bashizade, Hamid Sarbazi-Azad. 201-206 [doi]
• Design optimization of polyphase digital down converters for extremely high frequency wireless communicationsGain Kim, Raffaele Capoccia, Yusuf Leblebici. 207-212 [doi]
• Dual-mode double precision / two-parallel single precision floating point multiplier architectureManish Kumar Jaiswal, Hayden Kwok-Hay So. 213-218 [doi]
• Hardware implementation of real-time multiple frame super-resolutionKerem Seyid, Sebastien Blanc, Yusuf Leblebici. 219-224 [doi]
• Timing and robustness analysis of Pulsed-Index protocols for single-channel IoT communicationsShahzad Muzaffar, Ibrahim M. Elfadel. 225-230 [doi]
• A time interleaved DAC sharing SAR Pipeline ADC for ultra-low power camera front endsAnvesha Amaravati, Manan Chugh, Arijit Raychowdhury. 231-236 [doi]
• High-efficiency voltage regulation stage in energy harvesting systemsS. E. Kim, T. W. Kang, S. W. Kang, K. H. Park, M.-A. Chung. 237-240 [doi]
• A fully on-chip 25MHz PVT-compensation CMOS Relaxation OscillatorHamed Abbasizadeh, Behnam Samadpoor Rikan, Kang-Yoon Lee. 241-245 [doi]
• A time-window based approach for dynamic assertions mining on control signalsAlessandro Danese, Francesca Filini, Graziano Pravadelli. 246-251 [doi]
• Physical-based modeling and fast simulation of wireline linksJun Guo, Peng Liu 0016, Weidong Wang. 252-257 [doi]
• Trace signal selection methods for post silicon debuggingShridhar Choudhary, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita. 258-263 [doi]
• Timing attack on NEMS relay based design of AESSamah Mohamed Saeed, Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu. 264-269 [doi]
• A high efficiency rectifier for inductively power transfer applicationQiong Wei Low, Liter Siek, Mi Zhou. 270-273 [doi]
• Design and analysis of search algorithms for lower power consumption and faster convergence of DAC input of SAR-ADC in 65nm CMOSAnanthanarayanan Parthasarathy. 274-279 [doi]
• Efficient signature-based sub-circuit matchingAmir Masoud Gharehbaghi, Masahiro Fujita. 280-285 [doi]
• Reversible circuit rewriting with simulated annealingNabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, Rolf Drechsler. 286-291 [doi]
• A hybrid embedded compression codec engine for ultra HD video applicationSeongMo Park, Kyungjin Byun, Nak-Woong Eum. 292-296 [doi]
• A new sizing approach for lifetime improvement of nanoscale digital circuits due to BTI agingAndres F. Gomez, Víctor H. Champac. 297-302 [doi]
• Virtual prototype based on Aldebarn CPU coreJae-Jin Lee, Chan Kim, Kyungjin Byun, NakWoong Eum. 303-306 [doi]
• A generic clock controller for low power systems: Experimentation on an AXI busChadi Al Khatib, Claire Aupetit, Cyril Chevalier, Chouki Aktouf, Gilles Sicard, Laurent Fesquet. 307-312 [doi]
• Fast global interconnnect driven 3D floorplanningArtur Quiring, Markus Olbrich, Erich Barke. 313-318 [doi]
• Filtering dirty data in DRAM to reduce PRAM writesHyunsun Park, Chanha Kim, Sungjoo Yoo, Chanik Park. 319-324 [doi]
• On the estimation of assertion interestingnessTara Ghasempouri, Graziano Pravadelli. 325-330 [doi]
• Hardware/software partitioning of embedded System-on-Chip applicationsJia-Wei Tang, Yuan Wen Hau, Muhammad N. Marsono. 331-336 [doi]
• Exploiting scalable CGRA mapping of LU for energy efficiency using the Layers architectureZoltán Endre Rákossy, Dominik Stengele, Gerd Ascheid, Rainer Leupers, Anupam Chattopadhyay. 337-342 [doi]
• Dynamic migratory selection strategy for adaptive routing in mesh NoCsJohn Jose, Joe Augustine, Sijin Sebastian. 343-348 [doi]
• A cluster-based reliability- and thermal-aware 3D floorplanning using redundant STSVsYing-Jung Chen, Shanq-Jang Ruan. 349-354 [doi]
• Trace Buffer Attack: Security versus observability study in post-silicon debugYuanwen Huang, Anupam Chattopadhyay, Prabhat Mishra. 355-360 [doi]