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10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm

Seheon Jang, Munjae Chae, Hangi Park, Chanwoong Hwang, Jaehyouk Choi. 10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm. In IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024. pages 190-192, IEEE, 2024. [doi]

Authors

Seheon Jang

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Munjae Chae

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Hangi Park

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Chanwoong Hwang

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Jaehyouk Choi

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