Seheon Jang, Munjae Chae, Hangi Park, Chanwoong Hwang, Jaehyouk Choi. 10.2 A 5.5μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm. In IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024. pages 190-192, IEEE, 2024. [doi]
Abstract is missing.