8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment

Tae-Kwang Jang, Seokhyeon Jeong, Dongsuk Jeon, Kyojin David Choo, Dennis Sylvester, David Blaauw. 8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment. In 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017. pages 148-149, IEEE, 2017. [doi]

@inproceedings{JangJJCSB17,
  title = {8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment},
  author = {Tae-Kwang Jang and Seokhyeon Jeong and Dongsuk Jeon and Kyojin David Choo and Dennis Sylvester and David Blaauw},
  year = {2017},
  doi = {10.1109/ISSCC.2017.7870304},
  url = {http://dx.doi.org/10.1109/ISSCC.2017.7870304},
  researchr = {https://researchr.org/publication/JangJJCSB17},
  cites = {0},
  citedby = {0},
  pages = {148-149},
  booktitle = {2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017},
  publisher = {IEEE},
  isbn = {978-1-5090-3758-2},
}