Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization

Hochang Jang, Deokjin Joo, Taewhan Kim. Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization. IEEE Trans. on CAD of Integrated Circuits and Systems, 30(1):96-109, 2011. [doi]

Abstract

Abstract is missing.