Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer. Test Time Reduction in EDT Bandwidth Management for SoC Designs. IEEE Trans. on CAD of Integrated Circuits and Systems, 32(11):1776-1786, 2013. [doi]
Abstract is missing.