FPGA-efficient phase-to-I/Q architecture

Ireneusz Janiszewski, Hermann Meuth, Bernhard Hoppe. FPGA-efficient phase-to-I/Q architecture. In Proceedings 2004 IEEE International SOC Conference, September 12-15, 2004, Hilton Santa Clara, CA, USA. pages 373-376, IEEE, 2004. [doi]

Authors

Ireneusz Janiszewski

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Hermann Meuth

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Bernhard Hoppe

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