New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams

Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar. New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams. In Zoran Stamenkovic, Witold A. Pleskacz, Jaan Raik, Heinrich Theodor Vierhaus, editors, 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2015, Belgrade, Serbia, April 22-24, 2015. pages 251-254, IEEE, 2015. [doi]

Authors

Artjom Jasnetski

This author has not been identified. Look up 'Artjom Jasnetski' in Google

Jaan Raik

This author has not been identified. Look up 'Jaan Raik' in Google

Anton Tsertov

This author has not been identified. Look up 'Anton Tsertov' in Google

Raimund Ubar

This author has not been identified. Look up 'Raimund Ubar' in Google