Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar. New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams. In Zoran Stamenkovic, Witold A. Pleskacz, Jaan Raik, Heinrich Theodor Vierhaus, editors, 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2015, Belgrade, Serbia, April 22-24, 2015. pages 251-254, IEEE, 2015. [doi]
@inproceedings{JasnetskiRTU15,
title = {New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams},
author = {Artjom Jasnetski and Jaan Raik and Anton Tsertov and Raimund Ubar},
year = {2015},
doi = {10.1109/DDECS.2015.56},
url = {http://dx.doi.org/10.1109/DDECS.2015.56},
researchr = {https://researchr.org/publication/JasnetskiRTU15},
cites = {0},
citedby = {0},
pages = {251-254},
booktitle = {18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2015, Belgrade, Serbia, April 22-24, 2015},
editor = {Zoran Stamenkovic and Witold A. Pleskacz and Jaan Raik and Heinrich Theodor Vierhaus},
publisher = {IEEE},
isbn = {978-1-4799-6780-3},
}