Bit-Precise Formal Verification for SystemC Using Satisfiability Modulo Theories Solving

Lydia Jaß, Paula Herber. Bit-Precise Formal Verification for SystemC Using Satisfiability Modulo Theories Solving. In Marcelo Götz, Gunar Schirner, Marco Aurélio Wehrmeister, Mohammad Abdullah Al Faruque, Achim Rettberg, editors, System Level Design from HW/SW to Memory for Embedded Systems - 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, Foz do Iguaçu, Brazil, November 3-6, 2015, Proceedings. Volume 523 of IFIP Advances in Information and Communication Technology, pages 51-63, Springer, 2015. [doi]

Abstract

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