Rajeev Jayaraman, Frederica Darema. Error tolerance in parallel simulated annealing techniques. In Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988. pages 545-548, IEEE, 1988. [doi]
@inproceedings{JayaramanD88, title = {Error tolerance in parallel simulated annealing techniques}, author = {Rajeev Jayaraman and Frederica Darema}, year = {1988}, doi = {10.1109/ICCD.1988.25759}, url = {https://doi.org/10.1109/ICCD.1988.25759}, researchr = {https://researchr.org/publication/JayaramanD88}, cites = {0}, citedby = {0}, pages = {545-548}, booktitle = {Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988}, publisher = {IEEE}, isbn = {0-8186-0872-2}, }