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Tudor Jebelean. Systolic normalization of rational numbers. In International Conference on Application-Specific Array Processors, ASAP 1993, Proceedings, Venice, Italy, 25-27 October, 1993. pages 502-513, IEEE, 1993. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational NumbersBogdan Matasaru, Tudor Jebelean. fpl 2000: 810-813 [doi] Design of a systolic coprocessor for rational additionTudor Jebelean. asap 1995: 282-289 [doi]
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