Table of Contents

• Communication-minimal mapping of uniform loop nests onto distributed memory architecturesAlain Darte, Yves Robert. 1-14 [doi]
• The Xor embedding: An embedding of hypercubes onto rings and torusesAntonio González 0001, Miguel Valero-García. 15-28 [doi]
• Resource constrained scheduling of uniform algorithmLothar Thiele. 29-40 [doi]
• Mapping algorithms onto a multiple-chip data-driven arrayBilha Mendelson, Israel Koren. 41-52 [doi]
• Scheduling partitioned algorithms on processor arrays with limited communication supportsW. H. Chou, Sun-Yuan Kung. 53-64 [doi]
• Parallel processing architectures for rank order and stack filtersLori E. Lucke, Keshab K. Parhi. 65-76 [doi]
• A novel framework for multi-rate scheduling in DSP applicationsR. Govindarajan, Guang R. Gao. 77-88 [doi]
• Efficient scalable architectures for Viterbi decodersStefan Bitterlich, Heinrich Meyr. 89-100 [doi]
• A wavefront array processor for on the fly processing of digital video streamsGeorges Quénot, C. Coutelle, Jocelyn Sérot, Bertrand Zavidovique. 101-108 [doi]
• Subband filtering: Cordic modulation and systolic quadrature mirror filter treeEd F. Deprettere, Richard Heusdens, Hendrik Theunis. 109-123 [doi]
• On synthesizing application-specific array architectures from behavioral specificationsP. M. R. Jensen, K. Hermansen. 124-127 [doi]
• A simple expert system for the reasoning of systolic designsNam Ling. 128-131 [doi]
• RELACS for systolic programmingFrédéric Raimbault, Dominique Lavenier. 132-135 [doi]
• Data flow graphs granularity for overhead reduction within a PE in multiprocessor systemsM. Coli, P. Palazzari. 136-139 [doi]
• A massively parallel diagonal-fold array processorGerald G. Pechanek, José G. Delgado-Frias, Stamatis Vassiliadis. 140-143 [doi]
• Response-pipelined CAM chips - Building blocks for large associated arraysKanad Ghose. 144-147 [doi]
• An array-processor based architecture for classification problemsAntonella Bellettini, Alberto Ferrari, Roberto Guerrieri, Giorgio Baccarani. 148-151 [doi]
• Realization of a real time phasecorrelation chipset used in a hierarchical two step HDTV motion vector estimatorK. Müller, Frank Schirrmeister, Christian von Reventlow, Dirk Siebert, Jochen Reimers, C. Stoffers. 152-155 [doi]
• Asynchronous relaxation of locally-coupled automata networks, with application to parallel VLSI implementation of iterative image processing algorithmsPatricia Planet, Gilles Privat, Marc Renaudin. 156-159 [doi]
• Mapping arbitrary projections for volume rendering onto an array processorC. H. J. Ju, H. H. Taylor. 160-163 [doi]
• 3: A high performance signal processor for RADAR applicationsD. Camerani, M. Monacchi, R. Morbio. 164-167 [doi]
• COLUMNUS - An SIMD architecture for pattern recognition and simulations of statistical physicsMartin Neschen. 168-171 [doi]
• Processing of variable size images on a cellular array: Performance analysis with the Abingdon Cross BenchmarkMassimo Piccardi, Luigi di Stefano, Rita Cucchiara, Tullio Salmon Cinotti. 172-175 [doi]
• Matrix-matrix multiplications and fault tolerance on hypercube multiprocessorsYuh-Rong Leu, Ing-Yi Chen, Sy-Yen Kuo. 176-180 [doi]
• A highly-parallel match architecture for AI production systems using application-specific associative matching processorsChie Dou. 180-183 [doi]
• Reconfigurable hardware for molecular biology computing systemsEric Lemoine. 184-187 [doi]
• Systolic design of a new finite field division/inverse algorithmRichard Conway, J. Nelson. 188-191 [doi]
• Mapping Monte Carlo-Metropolis algorithm onto a double ring architectureGiovanni Danese, Ivo De Lotto, D. Dotti, D. Lanterna, Francesco Leporati, Remo Lombardi, S. Romano. 192-195 [doi]
• An application specific processor for implementing stack filtersBarun K. Kar, R. C. K. Kumar, Dhiraj K. Pradhan. 196-199 [doi]
• Low-power polygon renderer for computer graphicsWee-Chiew Tan, T.-Y. Meng. 200-213 [doi]
• Volume rendering by wavefront architectureShang-Hung Lin, S. Y. Kung. 214-225 [doi]
• Time-optimal visibility-related algorithms on meshes with multiple broadcastingDharmavani Bhagavathi, Venkatavasu Bokka, Himabindu Gurla, Stephan Olariu, James L. Schwing, Ivan Stojmenovic, Jingyuan Zhang. 226-237 [doi]
• A real-time systolic algorithm for on-the-fly hidden surface removalT. Risset, Siang Wun Song. 238-249 [doi]
• An efficient algorithm for image-template product on SIMD mesh connected computersHongchi Shi, Gerhard X. Ritter, Joseph N. Wilson. 250-260 [doi]
• A period-processor-time-minimal schedule for cubical mesh algorithmsChris J. Scheiman, Peter R. Cappello. 261-272 [doi]
• I/O data management on SIMD systolic arraysPatrice Frison, Dominique Lavenier, Frédéric Raimbault. 273-284 [doi]
• Optimum vectorization of scalable synchronous dataflow graphsSebastian Ritz, Matthias Pankert, V. Zivojinovic, Heinrich Meyr. 285-296 [doi]
• A new formulation of the mapping conditions for the synthesis of linear systolic arraysJ. Xue. 297-308 [doi]
• The PAPRICA SIMD array: Critical reviews and perspectivesFrancesco Gregoretti, Claudio Sansoè, Leonardo M. Reyneri, Alberto Broggi, Gianni Conte. 309-320 [doi]
• Formal descriptions, semantics and verification of VLSI array processorsZ. Zhou, N. Burleson. 321-332 [doi]
• An application-specific array architecture for feedforward with backpropagation ANNsQutaibah M. Malluhi, Magdy A. Bayoumi, T. R. N. Rao. 333-344 [doi]
• GENES IV: A bit-serial processing element for a built-model neural-network acceleratorPaolo Ienne, Marc A. Viredaz. 345-356 [doi]
• Implementation of large neural associative memories by massively parallel array processorsAlfred Strey. 357-368 [doi]
• A fast, storage-efficient parallel sorting algorithmRichard P. Brent, Andrew Tridgell. 369-379 [doi]
• A practical constant time sorting networkRong Lin, Stephan Olariu. 380-391 [doi]
• Multi-rate transformation of directional affine recurrence equationsY. Zheng, S. Kiaei. 392-403 [doi]
• An algorithm for accurate data dependence testZ. Xing, W. Shang. 404-415 [doi]
• Synthesis of dedicated SIMD processorsMichel Auguin, Fernand Boéri, C. Carrière, G. Menez. 416-427 [doi]
• Efficient exploration of nonuniform space-time transformations for optimal systolic array synthesisDonald G. Baltus, Jonathan Allen. 428-441 [doi]
• Node merging: A transformation on bit-level dependence graphs for efficient VLSI array designBongjin Jung, Wayne P. Burleson. 442-453 [doi]
• Heterogeneous BISR techniques for yield and reliability enhancement using high level synthesis transformationsMiodrag Potkonjak, Lisa M. Guerra, Jan M. Rabaey. 454-465 [doi]
• Digit systolic algorithms for fine-grain architecturesChetana Nagendra, Robert Michael Owens, Mary Jane Irwin. 466-477 [doi]
• Reduced area multipliersK'Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr.. 478-489 [doi]
• A novel architecture for a decision-feedback equalizer using extended signal-digit feedbackB. Koppenhofer. 490-501 [doi]
• Systolic normalization of rational numbersTudor Jebelean. 502-513 [doi]
• Systolic evaluation of functions: Digit-level algorithm and realizationS. P. Johansen. 514-525 [doi]
• Design of a VLSI circuit for on-line evaluation of several elementary functions using their Taylor expansionsJean-Claude Bajard, Alain Guyot, Jean-Michel Muller, Ali Skaf. 526-535 [doi]
• VLSI array synthesis for polynomial GCD computationY. Jeong, W. Burleson. 536-547 [doi]
• An optimal algo-tech-cuit for the knapsack problemRumen Andonov, Sanjay Rajopadhye. 548-559 [doi]
• Efficient architecture of a programmable block matching processorL. De Vos, M. Schobinger. 560-571 [doi]
• A 1D linearly expandable interconnection network performance analysisDominique Houzet, K. Fatni. 572-582 [doi]
• A CAD tool for electromagnetic simulation on the associative string processorD. P. Rodohan, S. R. Saunders. 583-592 [doi]