Young-Jin Jeon, Joong-Ho Lee, Hyun-Chul Lee, Kyo Won Jin, Kyeong-Sik Min, Jin-Yong Chung, Hong June Park. A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs. J. Solid-State Circuits, 39(11):2087-2092, 2004. [doi]
@article{JeonLLJMCP04,
title = {A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs},
author = {Young-Jin Jeon and Joong-Ho Lee and Hyun-Chul Lee and Kyo Won Jin and Kyeong-Sik Min and Jin-Yong Chung and Hong June Park},
year = {2004},
doi = {10.1109/JSSC.2004.835809},
url = {https://doi.org/10.1109/JSSC.2004.835809},
researchr = {https://researchr.org/publication/JeonLLJMCP04},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {39},
number = {11},
pages = {2087-2092},
}