A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs - researchr publication

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Young-Jin Jeon, Joong-Ho Lee, Hyun-Chul Lee, Kyo Won Jin, Kyeong-Sik Min, Jin-Yong Chung, Hong June Park. A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs. J. Solid-State Circuits, 39(11):2087-2092, 2004. [doi]

Abstract is missing.

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