Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic. Floorplan-based FPGA interconnect power estimation in DSP circuits. In Chung-Kuan Cheng, Sherief Reda, editors, The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings. pages 53-60, ACM, 2009. [doi]
Abstract is missing.