Niraj K. Jha. Testing for multiple faults in domino-CMOS logic circuits. IEEE Trans. on CAD of Integrated Circuits and Systems, 7(1):109-116, 1988. [doi]
@article{Jha88,
title = {Testing for multiple faults in domino-CMOS logic circuits},
author = {Niraj K. Jha},
year = {1988},
doi = {10.1109/43.3138},
url = {http://doi.ieeecomputersociety.org/10.1109/43.3138},
tags = {testing, logic},
researchr = {https://researchr.org/publication/Jha88},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {7},
number = {1},
pages = {109-116},
}