A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code

Kai-Yuan Jheng, Shyh-Jye Jou, An-Yeu Wu. A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code. In ISCAS (4). pages 293-296, 2004.

Abstract

Abstract is missing.