A low-power high-speed 32/33 prescaler based on novel divide-by-4/5 unit with improved true single-phase clock logic

Song Jia, Shilin Yan, Yuan Wang, Ganggang Zhang. A low-power high-speed 32/33 prescaler based on novel divide-by-4/5 unit with improved true single-phase clock logic. In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015. pages 890-893, IEEE, 2015. [doi]

@inproceedings{JiaYWZ15,
  title = {A low-power high-speed 32/33 prescaler based on novel divide-by-4/5 unit with improved true single-phase clock logic},
  author = {Song Jia and Shilin Yan and Yuan Wang and Ganggang Zhang},
  year = {2015},
  doi = {10.1109/ISCAS.2015.7168777},
  url = {http://dx.doi.org/10.1109/ISCAS.2015.7168777},
  researchr = {https://researchr.org/publication/JiaYWZ15},
  cites = {0},
  citedby = {0},
  pages = {890-893},
  booktitle = {2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015},
  publisher = {IEEE},
  isbn = {978-1-4799-8391-9},
}