Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging

Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou. Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging. IEEE Trans. on CAD of Integrated Circuits and Systems, 28(2):272-284, 2009. [doi]

Abstract

Abstract is missing.