Combined transistor sizing with buffer insertion for timing optimization - researchr publication authors

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Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim. Combined transistor sizing with buffer insertion for timing optimization. In Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, CICC 1998, Santa Clara, CA, USA, May 11-14, 1998. pages 605-608, IEEE, 1998. [doi]

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