Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim. Combined transistor sizing with buffer insertion for timing optimization. In Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, CICC 1998, Santa Clara, CA, USA, May 11-14, 1998. pages 605-608, IEEE, 1998. [doi]
@inproceedings{JiangSBK98-0,
title = {Combined transistor sizing with buffer insertion for timing optimization},
author = {Yanbin Jiang and Sachin S. Sapatnekar and Cyrus Bamji and Juho Kim},
year = {1998},
doi = {10.1109/CICC.1998.695051},
url = {https://doi.org/10.1109/CICC.1998.695051},
researchr = {https://researchr.org/publication/JiangSBK98-0},
cites = {0},
citedby = {0},
pages = {605-608},
booktitle = {Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, CICC 1998, Santa Clara, CA, USA, May 11-14, 1998},
publisher = {IEEE},
isbn = {0-7803-4292-5},
}