Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins. A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators. In 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010. pages 1011-1014, IEEE, 2010. [doi]
@inproceedings{JiangWCSUM10-0,
title = {A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators},
author = {Yang Jiang and Kim-Fai Wong and Chen-Yan Cai and Sai-Weng Sin and Seng-Pan U and Rui Paulo Martins},
year = {2010},
doi = {10.1109/APCCAS.2010.5774943},
url = {http://dx.doi.org/10.1109/APCCAS.2010.5774943},
researchr = {https://researchr.org/publication/JiangWCSUM10-0},
cites = {0},
citedby = {0},
pages = {1011-1014},
booktitle = {2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010},
publisher = {IEEE},
isbn = {978-1-4244-7454-7},
}