Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins. A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators. In 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010. pages 1011-1014, IEEE, 2010. [doi]
Abstract is missing.