Performance effects of pipeline architecture on an FPGA-based binary32 floating point multiplier

Xianyang Jiang, Peng Xiao, Meikang Qiu, Gaofeng Wang. Performance effects of pipeline architecture on an FPGA-based binary32 floating point multiplier. Microprocessors and Microsystems, 37(8-D):1183-1191, 2013. [doi]

Abstract

Abstract is missing.