Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors

Lei Jiang, Bo Zhao, Youtao Zhang, Jun Yang 0002. Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors. In Patrick Groeneveld, Donatella Sciuto, Soha Hassoun, editors, The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012. pages 907-912, ACM, 2012. [doi]

@inproceedings{JiangZZY12,
  title = {Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors},
  author = {Lei Jiang and Bo Zhao and Youtao Zhang and Jun Yang 0002},
  year = {2012},
  doi = {10.1145/2228360.2228521},
  url = {http://doi.acm.org/10.1145/2228360.2228521},
  researchr = {https://researchr.org/publication/JiangZZY12},
  cites = {0},
  citedby = {0},
  pages = {907-912},
  booktitle = {The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012},
  editor = {Patrick Groeneveld and Donatella Sciuto and Soha Hassoun},
  publisher = {ACM},
  isbn = {978-1-4503-1199-1},
}