An energy-efficient and scalable eDRAM-based register file architecture for GPGPU

Naifeng Jing, Yao Shen, Yao Lu, Shrikanth Ganapathy, Zhigang Mao, Minyi Guo, Ramon Canal, Xiaoyao Liang. An energy-efficient and scalable eDRAM-based register file architecture for GPGPU. In Avi Mendelson, editor, The 40th Annual International Symposium on Computer Architecture, ISCA'13, Tel-Aviv, Israel, June 23-27, 2013. pages 344-355, ACM, 2013. [doi]

Authors

Naifeng Jing

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Yao Shen

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Yao Lu

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Shrikanth Ganapathy

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Zhigang Mao

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Minyi Guo

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Ramon Canal

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Xiaoyao Liang

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