Phase-Tolerant Latency Control for a Combination 512Mb 2.0Gb/s/pin GDDR3 and 2.5Gb/s/pin GDDR4 SDRAM - researchr publication authors

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Brian Johnson, Brent Keeth, Feng Lin, Hua Zheng. Phase-Tolerant Latency Control for a Combination 512Mb 2.0Gb/s/pin GDDR3 and 2.5Gb/s/pin GDDR4 SDRAM. In 2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007. pages 494-617, IEEE, 2007. [doi]

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