Brian Johnson, Brent Keeth, Feng Lin, Hua Zheng. Phase-Tolerant Latency Control for a Combination 512Mb 2.0Gb/s/pin GDDR3 and 2.5Gb/s/pin GDDR4 SDRAM. In 2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007. pages 494-617, IEEE, 2007. [doi]
@inproceedings{JohnsonKLZ07,
title = {Phase-Tolerant Latency Control for a Combination 512Mb 2.0Gb/s/pin GDDR3 and 2.5Gb/s/pin GDDR4 SDRAM},
author = {Brian Johnson and Brent Keeth and Feng Lin and Hua Zheng},
year = {2007},
doi = {10.1109/ISSCC.2007.373510},
url = {http://dx.doi.org/10.1109/ISSCC.2007.373510},
researchr = {https://researchr.org/publication/JohnsonKLZ07},
cites = {0},
citedby = {0},
pages = {494-617},
booktitle = {2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007},
publisher = {IEEE},
isbn = {1-4244-0853-9},
}