An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs

Alex K. Jones, Prithviraj Banerjee. An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs. In FPGA. pages 244, 2003. [doi]

@inproceedings{JonesB03:3,
  title = {An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs},
  author = {Alex K. Jones and Prithviraj Banerjee},
  year = {2003},
  doi = {10.1145/611817.611873},
  url = {http://doi.acm.org/10.1145/611817.611873},
  tags = {C++, context-aware},
  researchr = {https://researchr.org/publication/JonesB03%3A3},
  cites = {0},
  citedby = {0},
  pages = {244},
  booktitle = {FPGA},
}