FVCAG: A framework for formal verification driven power modeling and verification

Arun Joseph, Spandana Rachamalla, Rahul M. Rao, Anand Haridass, Pradeep Kumar Nalla. FVCAG: A framework for formal verification driven power modeling and verification. In Proceedings of the 2016 International Symposium on Low Power Electronics and Design, ISLPED 2016, San Francisco Airport, CA, USA, August 08 - 10, 2016. pages 260-265, ACM, 2016. [doi]

Authors

Arun Joseph

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Spandana Rachamalla

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Rahul M. Rao

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Anand Haridass

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Pradeep Kumar Nalla

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