CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models

Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas. CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models. IEEE Trans. VLSI Syst., 23(7):1254-1267, 2015. [doi]

Abstract

Abstract is missing.