Gate-Oxide Trapping Enabled Synaptic Logic Transistor

X. Ju, D. S. Ang. Gate-Oxide Trapping Enabled Synaptic Logic Transistor. In 2020 IEEE International Reliability Physics Symposium, IRPS 2020, Dallas, TX, USA, April 28 - May 30, 2020. pages 1-6, IEEE, 2020. [doi]

Authors

X. Ju

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D. S. Ang

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