X. Ju, D. S. Ang. Gate-Oxide Trapping Enabled Synaptic Logic Transistor. In 2020 IEEE International Reliability Physics Symposium, IRPS 2020, Dallas, TX, USA, April 28 - May 30, 2020. pages 1-6, IEEE, 2020. [doi]
@inproceedings{JuA20-0,
title = {Gate-Oxide Trapping Enabled Synaptic Logic Transistor},
author = {X. Ju and D. S. Ang},
year = {2020},
doi = {10.1109/IRPS45951.2020.9129338},
url = {https://doi.org/10.1109/IRPS45951.2020.9129338},
researchr = {https://researchr.org/publication/JuA20-0},
cites = {0},
citedby = {0},
pages = {1-6},
booktitle = {2020 IEEE International Reliability Physics Symposium, IRPS 2020, Dallas, TX, USA, April 28 - May 30, 2020},
publisher = {IEEE},
isbn = {978-1-7281-3199-3},
}