Min-Rank Conjecture for Log-Depth Circuits

Stasys Jukna, Georg Schnitger. Min-Rank Conjecture for Log-Depth Circuits. Electronic Colloquium on Computational Complexity (ECCC), 16:8, 2009. [doi]

Authors

Stasys Jukna

This author has not been identified. Look up 'Stasys Jukna' in Google

Georg Schnitger

This author has not been identified. Look up 'Georg Schnitger' in Google