The following publications are possibly variants of this publication:
- NANDFlashSim: Intrinsic latency variation aware NAND flash memory system modeling and simulation at microarchitecture levelMyoungsoo Jung, Ellis Herbert Wilson, David Donofrio, John Shalf, Mahmut T. Kandemir. mss 2012: 1-12 [doi]
- Write-Buffer-Aware Address Mapping for NAND Flash Memory DevicesSungmin Park, Hoyoung Jung, Hyoki Shim, Sooyong Kang, Jaehyuk Cha. mascots 2008: 377-378
- SARO: A State-Aware Reliability Optimization Technique for High Density NAND Flash MemoryMyungsuk Kim, Youngsun Song, Myoungsoo Jung, Jihong Kim. glvlsi 2018: 255-260 [doi]