Horng-Fei Jyu, Sharad Malik. Prediction of interconnect delay in logic synthesis. In 1995 European Design and Test Conference, ED&TC 1995, Paris, France, March 6-9, 1995. pages 411-417, IEEE Computer Society, 1995. [doi]
@inproceedings{JyuM95,
title = {Prediction of interconnect delay in logic synthesis},
author = {Horng-Fei Jyu and Sharad Malik},
year = {1995},
doi = {10.1109/EDTC.1995.470363},
url = {http://doi.ieeecomputersociety.org/10.1109/EDTC.1995.470363},
researchr = {https://researchr.org/publication/JyuM95},
cites = {0},
citedby = {0},
pages = {411-417},
booktitle = {1995 European Design and Test Conference, ED&TC 1995, Paris, France, March 6-9, 1995},
publisher = {IEEE Computer Society},
isbn = {0-8186-7039-8},
}