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Test and Verification Environment and Methodology for Vernier Time-to-Digital Converter Pixel Array

Lukasz A. Kadlubowski, Piotr Kmon. Test and Verification Environment and Methodology for Vernier Time-to-Digital Converter Pixel Array. In Muhammad Shafique 0001, Andreas Steininger, Lukás Sekanina, Milos Krstic, Goran Stojanovic, Vojtech Mrazek, editors, 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021. pages 137-140, IEEE, 2021. [doi]

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Lukasz A. Kadlubowski

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Piotr Kmon

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