Table of Contents

• Fully-integrated SPAD active quenching/resetting circuit in high-voltage 0.35-μ m CMOS for reaching PDP saturation at 650 nmAlija Dervic, Saman Kohneh Poushi, Horst Zimmermann. 1-5 [doi]
• EKV MOS Transistor Model For Ultra Low-Voltage Bulk-Driven IC DesignLukás Nagy, Daniel Arbet, Martin Kovác, Miroslav Potocný, Michal Sovcik, Viera Stopjaková. 6-10 [doi]
• Predictive Fault Grouping based on Faulty AC MatricesNicola Dall'Ora, Sadia Azam, Enrico Fraccaroli, André Alberts, Franco Fummi. 11-16 [doi]
• Synthesis of approximate circuits for LUT-based FPGAsZdenek Vasícek. 17-22 [doi]
• Approximate Multipliers for Optimal Utilization of FPGA ResourcesChristoph Niemann, Michael Rethfeldt, Dirk Timmermann. 23-28 [doi]
• Behavioral Model of Dot-Product Engine Implemented with 1T1R Memristor Crossbar Including AssessmentJianan Wen, Markus Ulbricht 0002, Eduardo Perez, Xin Fan 0003, Milos Krstic. 29-32 [doi]
• Q-Learning-based Routing Algorithm for 3D Network-on-ChipsNurettin Bölücü, Suleyman Tosun. 33-36 [doi]
• AdequateDL: Approximating Deep Learning AcceleratorsOlivier Sentieys, Silviu Filip, David Briand, David Novo, Etienne Dupuis, Ian O'Connor, Alberto Bosio. 37-40 [doi]
• A Model-Based Framework to Assess the Reliability of Safety-Critical ApplicationsLucas Matana Luza, Annachiara Ruospo, Alberto Bosio, Ernesto Sánchez 0001, Luigi Dilillo. 41-44 [doi]
• Efficient Neural Network Approximation via Bayesian ReasoningAlessandro Savino, Marcello Traiola, Stefano Di Carlo, Alberto Bosio. 45-50 [doi]
• A Benchmark Suite of RT-level Hardware Trojans for Pipelined Microprocessor CoresAleksa Damljanovic, Annachiara Ruospo, Ernesto Sánchez 0001, Giovanni Squillero. 51-56 [doi]
• Design and Implementation Strategy of Adaptive Processor-Based Systems for Error Resilient and Power-Efficient OperationMitko Veleski, Michael Hübner 0001, Milos Krstic, Rolf Kraemer. 57-62 [doi]
• Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive PipelinesRaghda El Shehaby, Andreas Steininger. 63-68 [doi]
• Accelerated Analysis of Simulation Dumps through Parallelization on Multicore ArchitecturesDavide Appello, Paolo Bernardi, A. Calabrese, S. Littardi, Giorgio Pollaccia, S. Quer, Vincenzo Tancorre, R. Ugioli. 69-74 [doi]
• Embedded Test Instrument for Intermittent Resistive Fault Detection at Chip Level and Its Reuse at Board LevelHassan Ebrahimi, Hans G. Kerkhoff. 75-80 [doi]
• On the Functional Test of Special Function Units in GPUsJuan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda. 81-86 [doi]
• Prevention and Detection Methods of Systematic Failures in the Implementation of SoC Safety Mechanisms not Covered by Regular Functional TestsDenis Dutey, Stephane Martin, Anne Merlande, Om Ranjan. 87-92 [doi]
• Emerging Technologies: Challenges and Opportunities for Logic SynthesisAlberto Bosio, Mayeul Cantan, Cédric Marchand 0002, Ian O'Connor, Petr Fiser, Arnaud Poittevin, Marcello Traiola. 93-98 [doi]
• PolyAdd: Polynomial Formal Verification of Adder CircuitsRolf Drechsler. 99-104 [doi]
• Logic Resynthesis of Majority-Based Circuits by Top-Down DecompositionSiang-Yun Lee, Heinz Riener, Giovanni De Micheli. 105-110 [doi]
• Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay FaultsJosef Strnadel. 111-114 [doi]
• Efficient Acceleration of Decision Tree Algorithms for Encrypted Network Traffic AnalysisRoman Vrána, Jan Korenek. 115-118 [doi]
• Enhanced Reliability of Fully Differential Difference Amplifier Through On-chip Digital CalibrationDavid Maljar, Michal Sovcík, Daniel Arbet, Viera Stopjaková. 119-122 [doi]
• HEIST: A Hardware Signal Fault Injection Methodology Enabling Feasible Software Robustness TestingMartin Skriver, Anders Stengaard Sørensen, Ulrik Pagh Schultz. 123-126 [doi]
• CLD: An Accurate, Cost-Effective and Scalable Run-Time Cache Leakage DetectorAmeer Shalabi, Tara Ghasempouri, Peeter Ellervee, Jaan Raik. 127-132 [doi]
• Development of On-Chip Calibration for Hybrid Pixel DetectorsPawel Skrzypiec, Robert Szczygiel. 133-136 [doi]
• Test and Verification Environment and Methodology for Vernier Time-to-Digital Converter Pixel ArrayLukasz A. Kadlubowski, Piotr Kmon. 137-140 [doi]
• A Parameterizable Chisel Generator of Numerically Controlled Oscillators for Direct Digital SynthesisVukan D. Damnjanovic, Marija L. Petrovic, Vladimir M. Milovanovic. 141-144 [doi]
• An Open-source Library of Large Integer Polynomial MultipliersMalik Imran, Zain Ul Abideen, Samuel Pagliarini. 145-150 [doi]
• High-speed stateful packet classifier based on TSS algorithm optimized for off-chip memoriesMichal Orsák, Tomás Benes. 151-156 [doi]
• Tutorial: Silicon Systems for Wireless LANZoran Stamenkovic, Hassen Aziza, Ernesto Sánchez 0001, Alberto Bosio. 157-158 [doi]