Lukasz A. Kadlubowski, Piotr Kmon. Test and Verification Environment and Methodology for Vernier Time-to-Digital Converter Pixel Array. In Muhammad Shafique 0001, Andreas Steininger, Lukás Sekanina, Milos Krstic, Goran Stojanovic, Vojtech Mrazek, editors, 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021. pages 137-140, IEEE, 2021. [doi]
@inproceedings{KadlubowskiK21,
title = {Test and Verification Environment and Methodology for Vernier Time-to-Digital Converter Pixel Array},
author = {Lukasz A. Kadlubowski and Piotr Kmon},
year = {2021},
doi = {10.1109/DDECS52668.2021.9417054},
url = {https://doi.org/10.1109/DDECS52668.2021.9417054},
researchr = {https://researchr.org/publication/KadlubowskiK21},
cites = {0},
citedby = {0},
pages = {137-140},
booktitle = {24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021},
editor = {Muhammad Shafique 0001 and Andreas Steininger and Lukás Sekanina and Milos Krstic and Goran Stojanovic and Vojtech Mrazek},
publisher = {IEEE},
isbn = {978-1-6654-3595-6},
}