A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests

Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno. A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests. IEICE Transactions, 94-C(1):102-109, 2011. [doi]

@article{KaeriyamaKM11,
  title = {A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests},
  author = {Shunichi Kaeriyama and Mikihiro Kajita and Masayuki Mizuno},
  year = {2011},
  url = {http://search.ieice.org/bin/summary.php?id=e94-c_1_102},
  tags = {testing},
  researchr = {https://researchr.org/publication/KaeriyamaKM11},
  cites = {0},
  citedby = {0},
  journal = {IEICE Transactions},
  volume = {94-C},
  number = {1},
  pages = {102-109},
}