A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests

Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno. A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests. IEICE Transactions, 94-C(1):102-109, 2011. [doi]

Abstract

Abstract is missing.