Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion

Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu. Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion. IEEE Trans. on CAD of Integrated Circuits and Systems, 27(7):1241-1252, 2008. [doi]

Abstract

Abstract is missing.