A Transaction Processing Architecture for Effective Load Balancing Utilizing High Speed Bus - researchr publication bibtex

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Tetsuro Kakeshita, Susumu Kubo. A Transaction Processing Architecture for Effective Load Balancing Utilizing High Speed Bus. In CODAS. pages 376-379, 1996.

@inproceedings{KakeshitaK96,
  title = {A Transaction Processing Architecture for Effective Load Balancing Utilizing High Speed Bus},
  author = {Tetsuro Kakeshita and Susumu Kubo},
  year = {1996},
  tags = {architecture},
  researchr = {https://researchr.org/publication/KakeshitaK96},
  cites = {0},
  citedby = {0},
  pages = {376-379},
  booktitle = {CODAS},
}

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