High-level design verification using Taylor Expansion Diagrams: first results - researchr publication authors

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Priyank Kalla, Maciej J. Ciesielski, Emmanuel Boutillon, Eric Martin 0001. High-level design verification using Taylor Expansion Diagrams: first results. In Seventh IEEE International High-Level Design Validation and Test Workshop 2002, Cannes, France, October 27-29, 2002. pages 13-17, IEEE Computer Society, 2002. [doi]

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