Abstract is missing.
- VHDL-based simulation environment for Proteo NoCDavid A. Sigüenza-Tortosa, Jari Nurmi. 1-6 [doi]
- Slightly-off-specification failures in the time-triggered architectureAstrit Ademaj. 7-12 [doi]
- High-level design verification using Taylor Expansion Diagrams: first resultsPriyank Kalla, Maciej J. Ciesielski, Emmanuel Boutillon, Eric Martin 0001. 13-17 [doi]
- A 1000X speed up for properties completeness evaluationA. Castelnuovo, Andrea Fedeli, Alessandro Fin, Franco Fummi, Graziano Pravadelli, Umberto Rossi, F. Sforza, Franco Toto. 18-22 [doi]
- Checking temporal properties in SystemC specificationsAxel G. Braun, Joachim Gerlach, Wolfgang Rosenstiel. 23-27 [doi]
- High level validation of next-generation microprocessorsBob Bentley. 31-35 [doi]
- Top-level validation of system-on-chip in Esterel StudioGérard Berry, Lionel Blanc, Amar Bouali, Jerome Dormoy. 36-41 [doi]
- Practical experiences in functional simulation. An integrated method from unit to co-simulationKlaus-Dieter Schubert. 42-44 [doi]
- Formal analysis and validation of continuous-time Markov chain based system level power management strategiesGethin Norman, David Parker, Marta Z. Kwiatkowska, Sandeep K. Shukla, Rajesh K. Gupta. 45-50 [doi]
- Timed HW-SW cosimulation using native execution of OS and application SWIuliana Bacivarov, Sungjoo Yoo, Ahmed Amine Jerraya. 51-56 [doi]
- Setting break-points in distributed time-triggered architectureIdriz Smaili, Astrit Ademaj. 57-62 [doi]
- A hierarchical approach for designing dependable systemsMatteo Sonza Reorda, Massimo Violante, Nicola Mazzocca, Salvatore Venticinque, Andrea Bobbio, Giuliana Franceschinis. 63-68 [doi]
- Using Aspect-GAMMA in the design of embedded systemsMohammad Reza Mousavi, Giovanni Russello, Michel R. V. Chaudron, Michel A. Reniers, Twan Basten, Angelo Corsaro, Sandeep K. Shukla, Rajesh K. Gupta, Douglas C. Schmidt. 69-74 [doi]
- Generating concurrent test-programs with collisions for multi-processor verificationAllon Adir, Gil Shurek. 77-82 [doi]
- Adaptive test program generation: planning for the unplannedAllon Adir, Roy Emek, Eitan Marcus. 83-88 [doi]
- Breaking an application specific instruction-set processor: the first step towards embedded software testingJohn Dielissen, Benito Otero Mathijssen, Jos Huisken. 89-92 [doi]
- An effective and flexible approach to functional verification of processor familiesDavid Malandain, Pim Palmen, Matthew Taylor, Merav Aharoni, Yaron Arbetman. 93-98 [doi]
- Automatic functional test program generation for pipelined processors using model checkingPrabhat Mishra, Nikil Dutt. 99-103 [doi]
- Accelerated verification of RTL assertions based on satisfiability solversRanan Fraer, Shahid Ikram, Gila Kamhi, Tim Leonard, Abdel Mokkedem. 107-110 [doi]
- Alignability equivalence of synchronous sequential circuitsAmnon Rosenmann, Ziyad Hanna. 111-114 [doi]
- TRANS: efficient sequential verification of loop-free circuitsZurab Khasidashvili, John Moondanos, Ziyad Hanna. 115-120 [doi]
- Verification of a DSP IP cores by model checkingH. N. Nguyen, P. Koumou, Bernard Candaele, Michel Sarlotte, Christian Antoine, S. Emeriau. 121-124 [doi]
- Formal verification of embedded system designs at multiple levels of abstractionXi Chen, Fang Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe. 125-130 [doi]
- Prototyping of embedded digital systems from SDL language: a case studyCésar A. M. Marcon, Fabiano Hessel, Alexandre M. Amory, Luis H. L. Ries, Fernando Gehm Moraes, Ney Laert Vilar Calazans. 133-138 [doi]
- An equivalence checking methodology for hardware oriented C-based specificationsHiroshi Saito, Takaya Ogawa, Thanyapat Sakunkonchak, Masahiro Fujita, Takashi Nanya. 139-144 [doi]
- X-Gen: a random test-case generator for systems and SoCsRoy Emek, Itai Jaeger, Yehuda Naveh, Gadi Bergman, Guy Aloni, Yoav Katz, Monica Farkash, Igor Dozoretz, Alex Goldin. 145-150 [doi]
- Constructing reusable testbenchesAlex Wakefield, Bassam Jamil Mohd. 151-155 [doi]
- Taking the best out of two worlds: prototyping and hardware emulationMarkus Wannemacher, Mihai Munteanu, Sacha Perret, Rolf Singer. 156-161 [doi]
- A simple and effective compression scheme for test pins reductionMarie-Lise Flottes, Regis Poirier, Bruno Rouzeyre. 165-168 [doi]
- High-level and hierarchical test sequence generationGert Jervan, Zebo Peng, Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante. 169-174 [doi]
- Test generation for hardware-software covalidation using non-linear programmingFei Xin, Ian G. Harris. 175-180 [doi]
- Experimental validation of fault detection and fault tolerance mechanismsPiotr Gawkowski, Janusz Sosnowski. 181-186 [doi]