Algorithm Driven Power-Timing Optimization Methodology for CMOS Digital Circuits Considering PVTA Variations

Hema Sai Kalluru, Prasenjit Saha, Andleeb Zahra, Zia Abbas. Algorithm Driven Power-Timing Optimization Methodology for CMOS Digital Circuits Considering PVTA Variations. In IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021. pages 1-5, IEEE, 2021. [doi]

Abstract

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