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Design of Area-Power-Delay Efficient Square Root Carry Select Adder

Chetan Kamble, R. K. Siddharth, Shivnarayan Patidar, M. H. Vasantha, Nithin Y. B. Kumar. Design of Area-Power-Delay Efficient Square Root Carry Select Adder. In IEEE International Symposium on Smart Electronic Systems, iSES 2018 (Formerly iNiS), Hyderabad, India, December 17-19, 2018. pages 80-85, IEEE, 2018. [doi]

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Chetan Kamble

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R. K. Siddharth

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Shivnarayan Patidar

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M. H. Vasantha

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Nithin Y. B. Kumar

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