Chetan Kamble, R. K. Siddharth, Shivnarayan Patidar, M. H. Vasantha, Nithin Y. B. Kumar. Design of Area-Power-Delay Efficient Square Root Carry Select Adder. In IEEE International Symposium on Smart Electronic Systems, iSES 2018 (Formerly iNiS), Hyderabad, India, December 17-19, 2018. pages 80-85, IEEE, 2018. [doi]
@inproceedings{KambleSPVK18,
title = {Design of Area-Power-Delay Efficient Square Root Carry Select Adder},
author = {Chetan Kamble and R. K. Siddharth and Shivnarayan Patidar and M. H. Vasantha and Nithin Y. B. Kumar},
year = {2018},
doi = {10.1109/iSES.2018.00026},
url = {https://doi.org/10.1109/iSES.2018.00026},
researchr = {https://researchr.org/publication/KambleSPVK18},
cites = {0},
citedby = {0},
pages = {80-85},
booktitle = {IEEE International Symposium on Smart Electronic Systems, iSES 2018 (Formerly iNiS), Hyderabad, India, December 17-19, 2018},
publisher = {IEEE},
isbn = {978-1-5386-9172-4},
}